1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, it is suitable for an application to a semiconductor device in which a wiring on an upper layer and a wiring on a lower layer are connected to each other through a connection pillar.
2. Description of Related Art
In a main technique presently being used to connect a wiring on an upper layer and a wiring on a lower layer to each other through a connection pillar in a semiconductor device such as a silicon semiconductor integrated circuit device and the like, an interlayer insulation film is formed for covering the wiring on the lower layer, and a via hole (connection hole) is formed on the interlayer insulation film, and metal is then embedded in the via hole by using a sputtering method, a CVD method, and a plating method and the like, and the connection pillar is accordingly formed. Although differing from only the mechanism that a via hole and a wiring groove are embedded at the same time, even a so-called dual damascene method, which has been recently remarked in a copper wiring, is the technique belonging to the above-mentioned technique. Also, a pillar method of forming a connection pillar before forming an interlayer insulation film was proposed in the past. However, this technique forms the connection pillar by using a lift-off method and an etching method. Thus, it is only the alternative technique in the age when the formation of a deep hole was difficult.
However, even if the main technique in the above-mentioned conventional methods of forming the connection pillar continues using a material in Si oxide film system as the interlayer insulation film, it becomes difficult to embed the metal in association with the reduction in a diameter of the via hole and the increase in an aspect ratio of the via hole. Also, if a base film is required in order to improve the adhesion and grow the film, it is extremely difficult to make the film thickness thinner in proportion to the diameter of the via hole. This leads to a sharp increase in a wiring resistance of the via hole portion even if a metal of a low resistivity is used. Moreover, if the interlayer insulation film is replaced by a film of a low dielectric constant, it is difficult to suppress the so-called “poisoned via” (a phenomenon that the defect of the metal embedded by the sputtering method, the CVD method and the like is caused by out-gas from a side wall of the interlayer insulation film) as compared with the case of the usage of the interlayer insulation film in the Si oxide film system. Also, this technique results in a problem that each time the kind of the film of the low dielectric constant is changed, another suppressing method must be reconsidered.
Also, if the conventional pillar method employs the lift-off method, a lift-off film is limited to resist, and the embedding method is limited to the plating method (thus, a metal such as Al cannot be used by the typical method). After all, since only the embedded target is different, the above-mentioned problems cannot be solved. Also, in the case of the usage of the etching method, after the formation of a metal film on the entire surface of substrate, it is etched to then form the connection pillar. However, this method requires two adjustments of mask (the first adjustment of the mask is carried out in a lithography process for forming an opening in the interlayer insulation film on the lower layer wiring, and the second adjustment of the mask is carried out in a lithography process for etching the metallic film formed on the entire surface and then forming the connection pillar) in order to connect the connection pillar and the lower layer wiring. Hence, the defect caused by deviation in the mask adjustments is induced, which brings about a drop in the yield in the wiring process.
Therefore, in order to collectively solve the above-mentioned problems of the conventional techniques, the present invention provides a semiconductor device and the method of manufacturing the same. According to the present invention, it becomes possible to avoid the difficulty in the conventional technique for embedding the metal and the problem caused by the embedding operation, to settle the problem of the poisoned via and the problem of the wiring error caused by the mask adjustments, and to improve the yield and the reliability in the wiring process.